Two Week Main ISTE STTP On CMOS, Mixed Signal and Radio Frequency VLSI Design
30th January – 4th February 2017
A Two Week ISTE STTP on CMOS, Mixed Signal and Radio Frequency VLSI Design under the National Mission on Education through ICT (NMEICT), Government of India was organized by IIT Kharagpur, at Dronacharya College of Engineering, Greater Noida during 30th January to 4th February 2017 through ICT.
11 faculty members of different colleges including DGI, Greater Noida attended the workshop at Dronacharya Group of Institutions, Greater Noida.
The STTP was inaugurated by the Chief Guest, Padam Shree Prof. Deepak B. Phatak, Department of CSE, IIT Bombay. During the inaugural speech Prof. Phatak, highlighted the importance of VLSI Design and High Frequency IC Design.
Following dignitaries graced the inaugural ceremony:
- Prof. Raja Datta, Principal Investigator, T10KT, IIT Kharagpur
- Prof. Prabir Kumar Biswas, Co-Principal Investigator, T10KT, IIT Kharagpur
- Prof. T. K. Bhattacharya, Teaching faculty
- Prof. Indrajit Chakrabarti, Teaching faculty
- Prof. Mrigank Sharad, Teaching Faculty
Day 1: 30th January 2017
Prof. Mrigank Sharad started the session with the explanation on Transfer Characteristics of MOSFET. He described the small signal model of MOS transistor, its channel length modulation and mathematical equations. Prof. Sharad ended the session with explanation on Common Source Amplifier and its small signal model followed by the discussion session with remote centers.
Day 2: 31st January 2017
Prof. Indrajit Chakrabarti gave an overview of CMOS Inverter followed by dynamic CMOS logic circuit design and dynamic gate. He explained Cascading Problem in dynamic CMOS. He also gave a brief of Domino CMOS logic and further explained how to reduce delay in CMOS inverter.
Prof. Chakrabarti gave a detailed description of Low power signal processing circuit in which he explained static stand by power, sub threshold leakage, reverse biased and pseudo NMOS circuit. He explained the detailing of tree structured vector quantization (TSVQ), system level approach to minimize switched capacitance, and glitch reduction.
Prof. Chakrabarti ended the session by taking queries from the participants.
Day 3: 1st February 2017
Prof. T. K. Bhattacharya conducted a session on Basics of RF Design, in which he explained RF and application area of the RF-IC Design. He further Compared Analog and RF/MW, RF Circuits and Systems Design Issues. Prof. Bhattacharya described the effect of thermal Noise in MOSFET.
Day 4: 2nd February 2017
Prof. T. K. Bhattacharya began the session with a discussion on Low Noise Amplifier (LNA), its parameters, characteristics and Design consideration. He explained different structure of CMOS LNA, and gave a detailed description of LNA topologies with examples. He described power - constrained noise optimized device sizing in CS LNA, Cascode CG stage, CS Stage with matching through feedback. Prof. Bhattacharya explained other LNA Structures like Common gate LNA structure and Complementary LNA structure. He explained differential LNA, remedy of differential structure. He also showed the simulation results for Cascode CS LNA.
Dr. Indrajit Chakrabarti gave an overview of Video Compression. He further described in detail motion estimation, block matching for ME, and motion compensation. He also discussed the challenges in Motion Estimation and flow chart of Video Coding. half - pixel search hardware and the last topic on which he focused was ME algorithm by Combining Diamond Search and One - Bit Transformation.
Prof. T. K. Bhattacharya gave detailed explanation of mixers, its parameters, mixer design, and noise figure in single - sideband, noise folding and double-sideband (DSB) noise figure. He then discussed the implementation of single - ended passive mixer, and CMOS single - balanced mixer, its topologies, CMOS double-balanced mixer and mixer design procedure.
Day 5: 3rd February 2017
Prof. T. K. Bhattacharya conducted a session on Power Amplifier. He discussed the characteristics of power amplifier, its function and key specifications like maximum output power, power added efficiency, power gain, linearity and stability.
During the post lunch session Prof. Bhattacharya discussed CMOS Frequency Synthesizer. He also discussed the design of PLL and explained filter order.
Day 6: 4th February 2017
Prof. T. K. Bhattacharya explained the Layout Technique for Analog/RF Integrated Circuit, basics of analog/RF Layout and its design issues. He discussed the layout techniques of active devices, single transistor layout, parasitic in transistor and explained the Multiple Finger which reduces both gate resistance and parasitic capacitances. Prof. Bhattacharya gave a brief of orientation of devices, basic cell design and described about layout of Passive Devices.
Feedback and Valedictory
Feedback and Valedictory session of the workshop started after lunch at 2:30 PM on 4th February 2017. Prof. Adrijit Goswami, Co-Investigator, GIA was the Chief Guest during Valedictory.
Prof. S. K Varsani, Co- Principle investigator, Prof. Prabir Kumar Biswas, Co- Principle investigator, Prof. T. K. Bhattacharya, Prof. Indrajit Chakrabarti and Prof. Mrigank Sharad attended the feedback and valedictory ceremony. Participants of different remote centres gave their constructive feedback of the workshop. After the feedback session, Prof. T. K. Bhattacharya, Coordinator of the workshop, congratulated everyone for their whole-hearted participation in the workshop.
At Dronacharya Group of institutions, Greater Noida, workshop came to end with the distribution of Provisional Certificates to the participants by Prof. (Dr.) S. K. Bagga, Director - DGI Greater Noida.