Expert Lecture On

Introduction to Design Digital Circuits using Verilog HDL

23rd October 2024

IEEE Student Chapter, Dronacharya Group of Institutions, Greater Noida organized an expert lecture on “Introduction to Design Digital Circuits using Verilog HDL” on 23^rd October, 2024.  Mr. A. Kumar, Sr. Design Verification Engineer, NXP India was the keynote speaker of the session.

The objective of the lecture was to familiarize students about the Verilog HDL

The session was inaugurated by felicitating the Chief Guest by Prof. (Dr.) Arpita Gupta, Director DGI).Mr. A. Kumar started the session and explained very clearly that modules are the basic building blocks of Verilog designs with ports defining input and output connections and data types like wire and reg. Sequential logic involves memory elements like flip-flops and registers, which are typically described using always blocks triggered by clock edges. Verilog designs can be synthesized to actual hardware using synthesis tools, which convert Verilog code into gate-level netlists for physical hardware implementation. Key concepts in digital circuit design using Verilog include combinatorial logic, sequential logic, and finite state machines (FSM).

Takeaways from a session: Digital circuits are the backbone of modern electronic systems. They are used in a wide range of applications, from simple logic gates to complex microprocessors. Traditional methods of designing digital circuits were time-consuming and error-prone. However, with the advent of HDLs like Verilog, the design process has become much more efficient and reliable. Verilog HDL is a hardware description language used to model digital systems at various levels of abstraction. It allows designers to describe the behavior of a circuit, its structure, and its timing characteristics. Verilog is widely used in the industry for designing complex integrated circuits (ICs). Verilog HDL is a powerful tool that enables designers to create complex digital systems efficiently. By understanding the fundamentals of Verilog and following a structured design flow, engineers can design and implement a wide range of digital circuits.

The session was concluded with a vote of thanks delivered by Prof. Sanghamitra V. Arora, Head of the Departments of ECE, EEE, and ECZ at DGI, Greater Noida. The session was deemed highly fruitful and received praise from both students and faculty members. Attendees appreciated the engaging and passionate presentation, which highlighted numerous research opportunities, making it a valuable learning experience for everyone involved.