QEEE Session on
Combinational and Sequential Circuit Design - Digital IC Design
14th, 15th & 16th September 2016
QEEE Session on 'Combinational and Sequential Circuit Design - Digital IC Design' was organized by IIT, Madras under D2S (Direct to Student) Program at Dronacharya Group of Institutions, Greater Noida during 14th - 16th September 2016. The session was scheduled for B. Tech. (ECE) Final Year students. Dr. Nitin Chandrachoodan (IIT, Madras) was the resource person in this program. The program at DGI, Greater Noida was coordinated by Ms. Shailika Sharma (Assistant Professor, Department of ECE).
Day 1: 14th September 2016
The First session started with the lecture of Dr. Nitin Chandrachoodan. He started with static CMOS design of combinational circuit elements. He also explained Propagation Delay and Power Consumption. He discussed PMOS and NMOS fabrication steps and its advantages & disadvantages. He explained the Static CMOS Circuits using Pull - Up and Pull - Down set up. He discussed Glitch problem of Dynamic CMOS Logic and Dynamic CMOS Rules and explained Sizing problem of CMOS Domino Logic in detail. Session ended with Questionnaire.
Day 2: 15th September 2016
Dr. Nitin Chandrachoodan started lecture with the basics of Timing Analysis of CMOS Inverter and its working. Basic Voltage Transfer Characteristic of CMOS inverter was discussed with modes of MOSFETs. He later explained the Static and Dynamic Latches in Digital Integrated Circuit. He explained storage in a Static Sequential Circuit relies on the concept that a Cross - Coupled Inverter and principle for it. He discussed major disadvantage of the Static Gate. He also explained Latch-Based Systems such as NORA-CMOS - A Logic Style for Pipelined Structures, CMOS SRAM Cell, CMOS DRAM Cell and Latch-Based Sense Amplifier (DRAM).
Day 3: 16th September 2016
The third session started with a discussion on Combinational Modules of Adders and Latch-Based Shift Register. Dr. Chandrachoodan said Modern VLSI favors adder designs which have compact carry chains and adder delay is dominated by carry chain. He explained how various adder architectures differ from each other in carry generation circuit like Ripple Carry Adder, Carry-Look Ahead Adder, Carry-Select Adder, Carry Skip Adder, Manchester Carry Chain and Serial Adder.
The program ended with the Q&A Session.